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ASAHI KASEI
[AKD4632-A]
AKD4632-A
AK4632 Evaluation board Rev.0
GENERAL DESCRIPTION AKD4632-A is an evaluation board for the AK4632, 16bit mono CODEC with MIC/SPK/VIDEO amplifier. The AKD4632-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). AKD4632-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4632-A --- Evaluation board for AK4632 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for serial control mode
AVDD DVDD SVDD VVDD GND 3.3V Regulator
5V
MIC-Jack MIC
Control Data 10pin Header
BEEP/MIN/MOUT AOUT SPK-Jack
DSP
AK4632
10pin Header
VIN AK4114 VOUT
Opt In Opt Out
Clock Gen
Figure 1. AKD4632-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4632-A]
Evaluation Board Manual Operation sequence
1) Set up the power supply lines. 1-1) When AVDD, DVDD, SVDD, VVDD and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, VVDD and VCC jack should be open.). See "Other jumper pins set up (page 10)". [REG] [AVDD] [DVDD] [SVDD] [VVDD] [VCC] [AVSS] [AGND] [DGND] (red ) (orange) (orange) (blue) (blue) (orenge) (black) (black) (black) = 5V = open = open = open = open = open = 0V = 0V = 0V
: 3.3V is supplied to AVDD of AK4632 from regulator. : 3.3V is supplied to DVDD of AK4632 from regulator. : 3.3V is supplied to SVDD of AK4632 from regulator. : 3.3V is supplied to VVDD of AK4632 from regulator. : 3.3V is supplied to logic block from regulator. : for analog ground : for analog ground : for logic ground
1-2) When AVDD, DVDD, SVDD, VVDD and VCC are not supplied from the regulator. (AVDD, DVDD, SVDD, VVDD and VCC jack should be junction.) See "Other jumper pins set up (page 10)". [REG] [AVDD] [DVDD] [SVDD] [VVDD] [VCC] [AVSS] [AGND] [DGND] (red) (orange) (orange) (blue) (blue) (orenge) (black) (black) (black) = "REG" jack should be open. = 2.6 3.6V : for AVDD of AK4632 (typ. 3.3V) = 2.6 3.6V : for DVDD of AK4632 (typ. 3.3V) = 2.6 5.25V : for SVDD of AK4632 (typ. 3.3V, 5.0V) = 2.6 5.25V : for VVDD of AK4632 (typ. 3.3V, 5.0V) = 2.6 3.6V : for logic (typ. 3.3V) = 0V : for analog ground = 0V : for analog ground = 0V : for logic ground
Each supply line should be distributed from the power supply unit. AVDD and DVDD must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4632 and AK4114 should be reset once bringing SW1, 2 "L" upon power-up.
Evaluation mode
In case of AK4632 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4632 and AK4114. About AK4632's audio interface format, refer to datasheet of AK4632. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) (2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) (4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode (5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
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[AKD4632-A]
(1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4632 should be set to "0". X'tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X1. X'tal of 12.288MHz (Default) is set on the AKD4632-A. Set "No.8 of SW3" to "H". When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6 MCKI JP17 XTE JP18 MKFS
JP21 MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock Output frequency (16fs/32fs/64fs) of BICK should be set by "BCKO1-0 bit" in the AK4632. There is no necessity for set up JP19.
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When the AK4632 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4632-A]
(2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4632 should be set to "0". X'tal of 12.288MHz (Default) is set on the AKD4632-A. In this case, the AK4632 corresponds to PLL reference clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4632 is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then "MCKO bit" in the AK4632 is set to "1". When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6 MCKI
JP17 XTE
JP21 MCLK_SEL
JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When the AK4632 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI
JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4632 should be set to "1". JP6 (MCKI) should be open. b) Set up jumper pins of BICK clock When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17 XTE
JP21 MCLK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
XTL DIR EXT
INV
THR
DIR ADC
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn "256fs", "512fs", "1024fs" from left.
JP18 MKFS
JP18 MKFS
JP18 MKFS
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
And input frequency of BICK is set up in turn "16fs", "32fs", "64fs" from left.
JP19 BICK_SEL
JP19 BICK_SEL
JP19 BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
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[AKD4632-A]
c) Set up jumper pins of FCK clock When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP22 FCK_SEL
JP28 FCK
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When the AK4632 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI
JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4632 should be set to "0".
JP6 MCKI
JP17 XTE
JP21 MCLK_SEL
JP18 MKFS
XTL DIR EXT
256fs 512fs 1024fs
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28 FCK
JP22 FCK_SEL
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When D/A converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the following.
JP30 SDTI
JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock "MCKPD bit" in the AK4632 should be set to "0".
JP6 MCKI
JP17 XTE
JP21 MCLK_SEL
JP18 MKFS
XTL DIR EXT
256fs 512fs 1024fs
b) Set up jumper pins of BICK clock
JP20 BICK
JP27 BICK
JP29 BICK_INV
JP19 BICK_SEL
INV
THR
DIR ADC
INV
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28 FCK
JP22 FCK_SEL
DIR
ADC 2fs 1fs EXT
d) Set up jumper pins of DATA When A/D converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the following.
JP30 SDTI
JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4632 and AK4114 ON is "H", OFF is "L". No. Name ON ("H") OFF ("L") 1 DIF0 AK4114 Audio Format Setting 2 DIF1 See Table 2 3 CM2 Clock Operation Mode select 4 CM0 See Table 3 5 CM1 6 OCKS0 Master Clock Frequency Select See Table 4 7 OCKS1 8 M/S Master mode Slave mode Note. When the AK4632 is evaluated Master mode, "No.8 of SW3" is set to "H". Table 1. Mode Setting for AK4632 and AK4114
Register setting for AK4632 Audio Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit 0 1 1
DIF0 bit 1 0 1
DIF0 L L H
DIF1 L L L
DIF2 L H H
DAUX 24bit, Left justified 24bit, Left justified 24bit, I S
2
SDTO 16bit, Right justified 24bit, Left justified 24bit, I S
2
Default
Note. When the AK4632 is evaluated by using DIR/DIT of AK4114, "No.8 of SW3" is set to "L". Table 2. Setting for AK4114 Audio Interface Format UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 Default 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X'tal is not used as clock comparison for fs detection (i.e. XTL1,0= "1,1"), the X'tal is off. Table 3. Clock Operation Mode select No. 0 2 OCKS1 0 1 MCKO1 256fs 512fs MCKO2 256fs 256fs X'tal 256fs 512fs Mode 0 1 CM1 0 0 CM0 0 1
Default
Table 4. Master Clock Frequency Select (Stereo mode)
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[AKD4632-A]
Other jumper pins set up
1. JP1 (GND) OPEN SHORT 2. JP2 (AIN) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector "DGND" can be open.) : Connection between MICOUT pin and AIN pin of the AK4632. : No connection. : Connection.
3. JP3 (AVDD_SEL) : AVDD of the AK4632 REG : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default > AVDD : AVDD is supplied from "AVDD " jack. 4. JP8 (VVDD_SEL) : VVDD of the AK4632 AVDD : AVDD is supplied from "AVDD". < Default > VVDD : VVDD is supplied from "VVDD " jack. 5. JP9 (DVDD_SEL) : DVDD of the AK4632 AVDD : DVDD is supplied from "AVDD". < Default > DVDD : DVDD is supplied from "DVDD " jack. 6. JP10 (LVC_SEL) : Logic block of LVC is selected supply line. DVDD : Logic block of LVC is supplied from "DVDD". < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 7. JP11 (VCC_SEL) : Logic block is selected supply line. LVC : Logic is supplied from supply line of LVC. < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 8. JP4 (SVDD_SEL) : SVDD of the AK4632 REG : SVDD is supplied from the regulator ("SVDD" jack should be open). < Default > SVDD : SVDD is supplied from "SVDD " jack. 9. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114. MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4632. < Default > MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4632.
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ASAHI KASEI
[AKD4632-A]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. : Power control of AK4632. Keep "H" during normal operation.
[SW2] (PDN)
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4632 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4632-A
Connect PC
CSN CCLK CDTI
AKD4632
10 wire flat cable
10pin Connector
10pin Header
Figure 2. Connect of 10 wire flat cable
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[AKD4632-A]
Analog Input / Output Circuits
(1) Input Circuits a) MIC Input Circuit
J1 MIC-JACK
6 4 3
AVSS J3 MIC
JACK RCA
JP12 MIC_SEL INT
2 3 1
MR-552LS AVSS
Figure 3. MIC Input Circuit (a-1) Analog signal is input to INT pin via J1 connector.
JP12 MIC_SEL
RCA JACK
(a-2) Analog signal is input to INT pin via J3 connector.
JP12 MIC_SEL
RCA JACK
b) VIN Input Circuit
J6 VIN
C29 2 3 1 R23 75 VIN 0.1u
MR-552LS AVSS AVSS
Figure 4. VIN Input Circuit
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[AKD4632-A]
(2) Output Circuits a) AOUT Output Circuit
C28 AOUT
1
+
2
R20 220
1u
R21 20k AVSS
2 3 1
J5 AOUT
MR-552LS
AVSS
Figure 5. AOUT Output Circuit
b) VOUT Output Circuit
C18 1u + VSAG
1 2
JP7 11 00
VSAG_SEL
R22 75
+
VOUT
1
C17 47u
2
2 3 1
J7 VOUT
11 00 JP5 VOUT_SEL AVSS
R41 100k AVSS
MR-552LS
Figure 6. VOUT Output Circuit
(b-1) "DC Output" is output from J7 connector.
JP5 VOUT_SEL JP7 VSAG_SEL
00
11
00
11
(b-2) "SAG Trimming Circuit " is output from J7 connector.
JP5 VOUT_SEL JP7 VSAG_SEL
00
11
00
11
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ASAHI KASEI
[AKD4632-A]
C) SPK Output Circuit Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14 (SPN_SEL) should be open, or "PMSPK bit" in the AK4632 should be set to "0".
JP31 Dynamic J2 SPK-JACK
R15 10 SPP JP13
K
SVSS
3 4 6
D1
A
Dynamic(EXT) Piezo(EXT) Dynamic CN5 Dynamic(EXT) Piezo(EXT) Dynamic
2
SPK1 020S16 R
SVSS
DIODE ZENER D2
A K
SPP_SEL JP14
SVSS
DIODE ZENER
SPN_SEL
1
R17 10 SPN
L
Figure 7. SPK Output Circuit (C-1) "Dynamic Speaker" of external is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(C-2) "Piezo (Ceramic) Speaker" of external is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
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ASAHI KASEI
[AKD4632-A]
(C-3) Analog signal of SPP/SPN pins are output "Dynamic Speaker" on the evaluation (SPK1).
JP13 SPP_SEL JP14 SPN_SEL
JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(3) BEEP/MIN/MOUT Input and Output Circuit
C24 1u +
2
1
J4 BEEP/MIN/MOUT 2 3 1 MR-552LS AVSS
JP15 MIN/MOUT
MOUT C25 0.1u
OUT IN
R16 20k AVSS
2
C26 1u +
JP16
1
MOUT MIN BEEP
MIN R19 BEEP 20k
R18 47k AVSS
BEEP/MIN/MOUT
Figure 8. BEEP/MIN/MOUT Input and Output Circuit (3-1) Analog signal is input to MIN pin from J4 connector. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
(3-2) Analog signal of MOUT pin is output from J4 connector.
JP15 MIN/MOUT JP16 BEEP/MIN/MOUT MOUT MIN BEEP
IN
OUT
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ASAHI KASEI
[AKD4632-A]
(3-3) Analog signal of MOUT pin is input to MIN pin. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
(3-4) Analog signal is input to BEEP pin from J4 connector. JP15 JP16 BEEP/MIN/MOUT MIN/MOUT
MOUT MIN BEEP
IN
OUT
AKM assumes no responsibility for the trouble when using the above circuit examples.
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ASAHI KASEI
[AKD4632-A]
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4632-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4632-A by 10-line type flat cable (packed with AKD4632-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4632-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4632.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of the AK4632. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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ASAHI KASEI
[AKD4632-A]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 09h and 0Ah. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to the AK4632 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
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[AKD4632-A]
4. [SAVE] and [OPEN]
4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is "akr". 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4632. The file type is the same as [SAVE]. (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.
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[AKD4632-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks".
Figure 1. Window of [F3]
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[AKD4632-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
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ASAHI KASEI
[AKD4632-A]
6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks")
Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4632-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed.
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ASAHI KASEI
[AKD4632-A]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
- 24 -
2005/04
ASAHI KASEI
[AKD4632-A]
MEASUREMENT RESULTS EXAMPLE
1.AK4632 Mode: EXT mode (Slave) [Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * MCKI: 256fs, 512fs * BICK: 64fs * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=VVDD=3.3V,SVDD=3.3V/5.0V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] 1.ADC characteristics (MIC Gain = +20dB, IPGA=0dB, ALC1 = OFF, MIC IPGA Result MCKI clock 512fs 256fs Sampling Frequency 8kHz 16kHz 8kHz S/(N+D) (-1dBFS) 84.3dB 84.1dB 84.4dB D-Range (-60dBFS) 88.1dB 86.4dB 85.2dB S/N 88.1dB 86.3dB 88.2dB 2. DAC characteristics (AOUT) (DAC MCKI clock Sampling Frequency S/(N+D) (0dBFS) D-Range (-60dBFS) S/N 3. Speaker-Amp characteristics (DAC S/(N+D) AOUT, DVOL = 0dB) Result 512fs 8kHz 91.5dB 94.8dB 95.5dB MOUT 16kHz 89.6dB 92.0dB 93.5dB MIN 8kHz 90.8dB 94.5dB 95.0dB 256fs 16kHz 89.5dB 92.1dB 93.5dB ADC)
16kHz 84.0dB 86.3dB 86.3dB
SPP/SPN, ALC2=OFF) Result 69.6dB 73.5dB 73.2dB 73.8dB 90.4dB 91.7dB 90.6dB 91.0dB
S/N
SVDD=3.3V RL=8 SVDD=5.0V RL=10, CL=3uF SVDD=3.3V RL=8 SVDD=5.0V RL=10, CL=3uF ADC DAC AOUT)
SPKG1-0 = "00" (-0.5dBFS) SPKG1-0 = "01" (-0.5dBFS) SPKG1-0 = "10" (-0.5dBFS) SPKG1-0 = "11" (-0.5dBFS) SPKG1-0 = "00" SPKG1-0 = "01" SPKG1-0 = "10" SPKG1-0 = "11"
4. Loop-back (MIC
Result MCKI clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N 512fs 8kHz 84.2dB 88.4dB 88.4dB 16kHz 83.2dB 85.9dB 86.0dB 8kHz 84.2dB 87.0dB 87.0dB 256fs 16kHz 83.4dB 85.9dB 86.0dB
- 25 -
2005/04
ASAHI KASEI
[AKD4632-A]
2.AK4632 Mode: PLL SLAVE mode
[Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] 2-1. PLL Reference clock : BICK or FCK pin Loop-back (MIC ADC DAC AOUT) Result PLL Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N 1fs (FCK pin) 8kHz 16kHz 75.3dB 78.6dB 86.5dB 86.0dB 86.5dB 85.9dB 16fs (BICK pin) 8kHz 16kHz 84.7dB 83.8dB 87.7dB 85.9dB 87.6dB 85.8dB
2-2. PLL Reference clock : MCKI pin
Loop-back (MIC ADC DAC AOUT) Result 12.288MHz 8kHz 16kHz 84.7dB 83.8dB 87.4dB 85.8dB 88.0dB 85.8dB
PLL Reference clock Sampling Frequency S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N
3.AK4632 Mode: PLL MASTER mode
[Measurement condition] * Measurement unit: ROHDE & SCHWARZ, UPD05 * MCKI: 12.288MHz * BICK: 16fs * Bit: 16bit * Sampling Frequency: 8kHz & 16kHz * Measurement Frequency: 20 3.4kHz (fs=8kHz), 20 8kHz (fs=16kHz) * Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V * Temperature: Room * Input Frequency: 1kHz [Measurement Results] Loop-back (MIC ADC DAC AOUT) Result 8kHz 84.2dB 86.9dB 87.0dB
S/(N+D) (-1dBFS) D-Range (-60dBFS) S/N
16kHz 83.3dB 85.0dB 85.0dB
- 26 -
2005/04
ASAHI KASEI
[AKD4632-A]
4.PLOT DATA (EXT Slave mode) 4-1.ADC (MIC ADC) PLOT DATA
Figure 1. THD+N vs. Input Level
Figure 2. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Ceramic Condenser
In this case, a ceramic condenser is used as C7 between MICOUT pin as AIN pin on the AKD4632-A.As the performance of Ceramic condenser is not so good about low frequency signal. Refer to Figure 3 about the performance of AK4632.
- 27 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 3. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Film Condenser
Figure 4. Linearity
- 28 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 5. Frequency Response (by the board of AKD4632-A) High pass filter is composed by the input impedance of AIN pin and C7 between MICOUT pin and AIN pin. Refer to Figure 6 about frequency response of AK4632's ADC.
Figure 6. Frequency Response (AIN
ADC)
- 29 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 7. FFT Plot ( Input level=-1.0dBFS)
Figure 8. FFT Plot ( Input level=-60.0dBFS )
- 30 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 9. FFT Plot ( "0" data input )
- 31 -
2005/04
ASAHI KASEI
[AKD4632-A]
4-2. DAC (DAC
AOUT) PLOT DATA
Figure 10. THD+N vs. Input Level
Figure 11. THD+N vs. Input Frequency (Input Level = 0dBFS)
- 32 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 12. Linearity
Figure 13. Frequency Response
- 33 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 14. FFT Plot ( Input level=0dBFS )
Figure 15. FFT Plot ( Input level=-60.0dBFS )
- 34 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 16. FFT Plot ( "0" data input )
- 35 -
2005/04
ASAHI KASEI
[AKD4632-A]
4-3. VIDEO PLOT DATA [Measurement condition] * Measurement unit: Tektronix VM700T Video Measurement set * Power Supply: AVDD=DVDD=SVDD=3.3V,VVDD=3.3V * Temperature: Room * Input Frequency: 1kHz
4-3-1. S/N * Measurement Frequency: 100kH 6MHz
Figure 1. Noise Spectrum
- 36 -
2005/04
ASAHI KASEI
[AKD4632-A]
4-3-2. SAG
Figure 2. Field Time Distortion (DC Output, SAGC bits = "00")
Figure 3. Field Time Distortion (SAG Trimming 47F+ 1.0uF, SAGC bits = "10")
- 37 -
2005/04
ASAHI KASEI
[AKD4632-A]
Figure 4. Field Time Distortion (SAG Trimming 100F+ 2.2uF, SAGC bits = "11")
4-3-3. Vector
* Input signal: 75% color
Figure 5. 75% Color Vector (SAG Trimming 47F+ 1.0uF, SAGC bits = "10")
- 38 -
2005/04
ASAHI KASEI
[AKD4632-A]
Revision History
Date 04/11/24 05/04/05 Manual Revision KM075601 KM075602 Board Revision 0 0 Reason First Edition Change Contents
"Control Software Manual" chapter is changed by version up of control software.
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 39 -
2005/04
A
B
C
D
E
REG_IN
T1 TA48033F
GND IN OUT 1
JP1 GND REG INT C2 0.1u AVSS SVSS MOUT BEEP AOUT C3 + 47u
2
E
C1 0.1u
E
AVSS AVSS CN1 32pin_4
32 31 30 29 28 27 26 25
REG T45_R
AVDD T45_O
DVDD T45_O
VVDD T45_BU
AVSS T45_BK
SVDD T45_BU
SVSS T45_BK
DGND T45_BK
1
1
1
1
1
1
1
REG_IN C4 2.2u
D
AVDD
DVDD
VVDD AVSS
SVDD SVSS
2
C5 0.1u
1
AVSS
32 31
30
1
29
28
27
26
U1 R2 C8 4.7n CN2 AVDD L1
1 1 2
VCOM
MIC
AIN
MICOUT
AOUT
REG JP3 AVDD_SEL
1
MOUT
BEEP
MPI
10k
25
VCOC
AVSS
1 2 1 2
2
3
1
AVSS
SVDD
22
C13 47u
C
2
1
AVSS
4
AVSS
R5 (short)
SPN 20
R4 (open)
1
SAGC00 SAGC11 SAGC00
7 2 1 6
AVDD JP8 AVDD VVDD_SEL L3
1 2
VOUT
6 7
C17 47u +
VOUT
MCKO
19
19 18
4632_MCKO SVSS 4632_MCKI
VVDD
PDN VVDD
8
SAGC11 2 1 JP7 C18 1u VSAG_SEL
8
VSAG
MCKI
18
JP6 MCKI
17
AVSS
PDN DVDD SDTO CCLK CDTI BICK SDTI CSN FCK DVSS 17
C19 47u
1
+
2
(short)
32pin_1 R6 51
32pin_3
AVSS
B
C20 0.1u
B
10
11
12
13
14
15
AVDD JP9 AVDD DVDD_SEL L4
1 2
16
9
R7 51 R14 10 DVDD DVDD R40 (short) DVDD JP10 LVC_SEL
R8 51
R9 51
R10 51
R11 51
R12 470
R13 470
+
1
2
AVSS
DVDD
C21 10u
C22 47u
1
+
2
(short)
10
11
12
13
14
15
LVC AVSS VCC
32pin_2 JP11 VCC_SEL 4632_SDTI CSN D3.3V VCC CCLK CDTI
4632_SDTO
VCC(3.3V) L5
A
LVC
2
4632_BICK
4632_FCK
1
DVDD
16
CN4
9
2
AVSS
VIN
5
JP5 VOUT_SEL
C23 47u
1
+
2
(short)
A
B
+
+
(short)
AVDD
2
AVDD
3
C14 10u
C15 0.1u
4 VVDD
R3 (short)
AK4632
SPP
21 21 20
5
VIN
C
+
C9 10u
+
C11 0.1u
2
REG
C10 0.1u
AVDD
+
R1 2.2k
C6 1u
2
C7 0.22u
JP2 AIN
1
+
D
MIN
24
CN3
SVSS 23 24
REG MIN SVDD SVSS JP4 REG SVDD_SEL
1
C12 10u
SVSS
23 22
L2
2
SVDD SPP SPN
(short)
C16 + 47u
C
+
A
Title Size Document Number
AKD4632
AK4632
Sheet
E
Rev
A3
Date:
D
0 1
of
Wednesday, August 18, 2004
5
A
B
C
D
E
J1 MIC-JACK
6 4 3
JP31 Dynamic J2 SPK-JACK
3 4 6
E
AVSS J3 MIC
JACK RCA
JP12 MIC_SEL INT SPP
R15 10
SVSS
E
2 3 1
D1
A K
JP13
MR-552LS AVSS C24 1u
2 1
Dynamic(EXT) Piezo(EXT) Dynamic CN5
SPK1 020S16 R
2
SVSS MOUT C25 0.1u SVSS
DIODE ZENER D2
A K
SPP_SEL JP14 Dynamic(EXT) Piezo(EXT) Dynamic
J4 BEEP/MIN/MOUT 2 3 1 MR-552LS
D
JP15 MIN/MOUT
+
OUT IN AVSS
R16 20k
DIODE ZENER
SPN_SEL
1
L R17 10
D
AVSS C26 1u
2 1
JP16
SPN MOUT MIN BEEP MIN R19 BEEP 20k
+ R18 47k AVSS
BEEP/MIN/MOUT
C28 + AOUT
1 2
R20 220 2 3 1
J5 AOUT
1u
R21 20k AVSS
MR-552LS
C
C
AVSS
J6 VIN
C29 2 3 1 R23 75 VIN 0.1u R41 100k VOUT
R22 75
2 3 1
J7 VOUT
MR-552LS AVSS AVSS
B
MR-552LS AVSS
AVSS
B
A
A
Title Size Document Number
AKD4632
Input/Output
Sheet
E
Rev
A3
Date:
A B C D
0 2
of
Wednesday, August 18, 2004
5
A
B
C
D
E
for 74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
D3.3V 12.288MHz X1
1 2
E
C30 0.1u
C31 0.1u
C32 0.1u
C33 0.1u
C34 0.1u
C35 0.1u
C36 0.1u
1
R24 1M
U2A
1 2 3
U2B
4
74HCU04 JP17 XTE C38 (open)
74HCU04 C39 (open)
D
2
+ C37 47u
E
D
EXT_MCLK
VCC
VCC JP18 MKFS
10 11
10
4
U4A 74AC74
Q 5 12 11 D CLK
U4B 74AC74
Q 9
PR
DIR_MCLK
C
XTL DIR EXT
JP21
R25 short
D CLK
PR
2 3
256fs 512fs 1024fs MCKO
U3
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
64fs 32fs 16fs EXT
JP19 BICK_SEL
THR
1 2
JP20 BICK EXT_BICK
CL
Q
6
CL
Q
8
INV U5A 74HC14
C
MCLK_SEL
13
1
74VHC4040 MCKO
2fs 1fs EXT
JP22 EXT_FCK FCK_SEL
J8 EXT/BICK
B
2 3 1 R26 51 AVSS JP23 EXT1
B
MR-552LS
J9 FCK
2 3 1 R27 51 AVSS JP24 EXT2
Title Size Document Number
A
MR-552LS
A
AKD4632
CLOCK
Sheet
E
Rev
A3
Date:
A B C D
0 3
of
Wednesday, August 18, 2004
5
A
B
C
D
E
C40 C41 0.1u 0.1u D3.3V
1
D3.3V L6 (short)
2
E
R28 10k U5B R29 470 C43 10u
2 1 4 3 6
K
PORT1
VCC GND OUT 3 2 1
C42 0.1u
U5C
5
3
C45 0.1u
C44 0.1u
2
1
TORX141
D3.3V
74HC14
74HC14
L
A
D3 HSU119
E
H SW1 DIR
+
C46 0.47u
R30 18k
48
47
46
45
44
43
42
41
40
39
38
D
DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1 M/S
SW3
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U6
VCOM
TEST1
AVSS
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
37
D
U7A
INT0 36 1 2
R31 1k
K
LED1 ERF
A
1
IPS0
D3.3V
74HC04
2 NC OCKS0 35
OCKS0
RP1
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
CM0 CM1 OCKS0 OCKS1 M/S
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
C
47k
C
6
NC
1
7
DIF2
AK4114
PDN
31
C47 (open)
XTI 30
X2 11.2896MHz
8 2 IPS1 XTO 29
C48 (open)
9
P/SN
DAUX
28
DAUX
10
XTL0
MCKO2
27
11
B
XTL1
BICK
26
DIR_BICK
B
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
DIR_SDTI
13
14
15
16
17
18
19
20
21
22
23
C49 0.1u +
C50 0.1u +
24
DIR_FCK
JP25 MCKO_SEL MCKO2 MCKO1 DIR_MCLK
1
2
1
2
C51 10u D3.3V D3.3V PORT2
A
C52 10u
IN VCC GND
3 2 1
A
D3.3V C53 0.1u
Title Size Document Number
TOTX141
AKD4632
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
0 4
of
Wednesday, August 18, 2004
5
A
B
C
D
E
U9
E
U8
LVC
20
1 11 Y8 A8 9
M/S
19
DIR
VCC
E
C54 0.1u
G GND 10
MCKO
12
Y7
A7
8
4632_MCKO RP2 RP3
7 6 5 4 3 2 1 2 A1 B1 18 7 6 5 4 3 2 1
4632_MCKI
13
Y6
A6
7
EXT_MCLK
3
DAUX
14
Y5
A5
6
4632_SDTO JP26 4632_SDTI DAC/LOOP 47k
A2
B2
17
4
4632_SDTI
15
Y4
A4
5 5
A3
B3
16
47k
16
D
Y3
A3
4
ADC
6
A4
B4
15
D
17
Y2
A2
3 7
A5
B5
14
18
Y1
A1
2 8
A6
B6
13
JP27 BICK
12
ADC DIR
EXT_BICK DIR_BICK
10
GND
G2
19
4632_BICK
A7
B7
C55 0.1u
20 VCC G1 1
4632_FCK
9
A8
B8
11
JP28 FCK
ADC DIR
EXT_FCK DIR_FCK
74LVC245 74LVC541
C
C
LVC + C56 47u
1
U10A
2
JP29 INV THR BICK_INV
2
1
74HC14
D3V
R32 R34 R36
10k 10k 10k
R33 R35 R37
470 470 470
U11
2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11
CSN CCLK CDTI PDN
4632_MCKI MCLK BICK FCK SDTI VCC
1 2 3 4 5
PORT3
10 9 8 7 6
PORT4
1 2 3 4 5 10 9 8 7 6
CSN CCLK CDTI
ROM
B
B
CTRL
74HC541
R38 D3V 10k ADC
D3V
K
DAUX
A
D4 HSU119
R39 10k U5D
9 8 11
JP30 SDTI DIR U5E
10
DIR_SDTI
74HC14 L
3 1
74HC14
U2C
5 6 13
U2F
12 9
U7D
8 3
U10B
4
H 74HCU04 SW2 PDN
2
74HCU04 U7B
3 4 11
74HC04 U7E
10 5
74HC14 U10C
6 11
A
C57 0.1u
U2D
9 8
U10E
10
A
74HCU04 U2E
11 10 5
74HC04 U7C
6 13
74HC04 U7F
12 9
74HC14 U10D
8 13
74HC14 U10F
12 Title Size Document Number
74HCU04
74HC04
74HC04
74HC14
74HC14
AKD4632
LOGIC
Sheet
E
Rev
A3
Date:
A B C D
0 5
of
Wednesday, August 18, 2004
5

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